1. Field of the Invention
The present invention relates in general to ceramic substrates and more specifically a ceramic substrate which is provided with a group of terminals for connection with an IC (integrated circuit) chip or chips by flip chip bonding or the like, or which is provided with a group of terminals which is so-called a ball-grid array or pin-grid array, for connection with an external circuit board.
2. Description of the Prior Art
Bonding which is so called face down bonding or flip chip bonding is known for joining the I/O (input/output) terminals of a high density integrated circuit, which high density integrated circuit requires a number of I/O terminals and has arranged on one side thereof the I/O terminals, directly and by fusion to the connecting terminals provided to a ceramic substrate for an IC package for instance. The terminals or pads of the ceramic substrate for mounting thereon such a flip-chip type integrated circuit having I/O terminals or bump contacts on the entire side surface thereof, have heretofore been arranged similarly to the I/O terminals of the integrated circuit chip and formed simply into a circular or square shape. That is, as shown in FIG. 6, the metallized layers 23 formed on a substrate 21 to constitute connecting terminals have, when observed in a plan view, a circular shape and have formed thereon plating layers or solder layers. In installation, the integrated circuit chip is laid upon the substrate in such a manner that the terminals of the integrated circuit chip coincide with the connecting terminals of the substrate, respectively, so that the terminals of the integrated circuit chip are soldered to the terminals of the substrate by fusing the solder pads previously formed on the terminals of the integrated circuit chip or on the terminals of the substrate.
Such a ceramic substrate is produced in the following manner. That is, a ceramic substrate having a circuit wiring and via-holes is produced by forming green sheets from ceramic powder such as alumina powder added with organic resin and solvent by a doctor blade method, screen-printing a metallic paste mainly composed of molybdenum and tungsten powder on the green sheets, forming through holes in the green sheets and filling the holes with the metallic paste, and thereafter laminating a plurality of the green sheets and co-firing them. That is, as shown in FIG. 7, a group of metallized pads 23 to serve as connecting terminals on the ceramic substrate 21 are formed by printing a metallic paste on the unfired or unsintered substrate (green sheets 25) in such a manner as to have a predetermined pitch and arrangement (i.e., pattern) that coincide with those of the terminals of the integrated circuit, and firing the paste together with the substrate (co-firing). The ceramic contracts or shrinks during sintering or firing, so the pattern of the metallized layers is determined on consideration of a predetermined rate of firing shrinkange (i.e., rate of shrinkage during sintering) so that the metallized layers of a predetermined size and arrangement (i.e., intervals thereof) are obtained after the sintering.
In the meantime, the rate of firing shrinkage of, for example, an alumina ceramic substrate is generally considered as being about 20% but should theoretically be constant provided that the conditions such as the material and composition are the same. However, it is in effect impossible to control the conditions such as the fineness of the starting material, the conditions of the furnace, the conditions of laminating and pressing the green sheets for obtaining a preform for a substrate, etc. in such a manner as to be completely constant, so a variation or fluctuation of the rate of firing shrinkage occurs though a little. It is generally considered as being a limit to reduce the variation (error) to about +0.3%. Accordingly, in designing of a substrate, a dimensional allowance is determined by considering a variation of the rate of firing shrinkage at such an amount. Due to this, for example in case a designed pitch of the metallized layers is 5 mm, it can become maximumly 5.015 mm and minimumly 4,985 after sintering of the substrate which are an upper limit and lower limit of the allowance, respectively.
Accordingly, as shown in FIG. 8, although the pitch "Ja" of the terminals of the integrated circuit chip "J" is just the same as a designed value, there is caused a misalignment (i.e., discrepancy) between the terminals of the substrate 21 and the integrated circuit chip "J" when the pitch of the metallized pads 23 of the substrate 21 is close to an upper limit or lower limit of an allowable range. This means that the more in number and the more in density the terminals of a small size are provided, the more the reliability on the connection of the terminals is decreased, thus causing a large problem in joining of a flip-chip type integrated circuit chip to a substrate. As a means for solving this problem, it will be considered that the metallized layers for constituting the terminals of the substrate, when observed in a plan view, is formed to have a circular shape of a larger diameter on consideration of a variation of the rate of firing shrinkage. However, when this is the case, the gap or space between the metallized layers becomes smaller, thus causing a problem that the rate of occurrence of short circuit defect is increased. Further, the larger the metallized layers for constituting the terminals of the substrate becomes, the more the amount of solder is lacked since, in case the integrated circuit chip has solder layers on the terminals thereof, the solder is caused to spread all over the areas of the terminals of the substrate. Conversely, in case the solder layers are formed on the terminals of the substrate, the amount of the solder of the substrate becomes larger, thus being liable to cause a short circuit defect at the time of joining of the substrate with an integrated circuit chip. Further, to make the metallized layers for constituting connecting terminals large-sized goes against the demand for reducing the distance between the terminals, i.e., the demand for a fine pitch between the terminals for enabling to increase the number of terminals of the integrated circuit chip and make the chip small-sized.